TTTC's
Electronic Broadcasting Service |
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Test Track at the April 20-24, 2009 |
CALL
FOR PAPERS |
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The Design, Automation and Test in Europe conference and exhibition is the main European event bringing together design automation researchers, users and vendors, as well as specialists in the design, test, and manufacturing of electronic systems and circuits. One of the tracks of DATE is devoted to Methods, Tools and Innovative Experiences in Testing Electronic Circuits and Systems. You are invited to submit your research contributions to the test track. This five-day event consists of a conference with plenary keynotes, regular papers, interactive presentations, panels and hot-topic sessions, tutorials, master courses and workshops, as well as a Designers’ Forum. DATE is also Europe’s leading commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services. Both the conference and the exhibition, together with the many user group meetings, fringe meetings, university booth and social events offer a wide variety of opportunities to meet and exchange information. |
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Test Topic Areas | |||
The test track is organised in six topics. These topics together with their chairs and area descriptions are given as follows. T1 System and Industrial Test Testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, board, system; Network-on-Chip test; system-level debug and validation; hardware/software system test; processor-based test; infrastructure IP; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies. T2 Design for Test and BIST Design for test, debug and manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures. T3 Test Generation, Simulation and Diagnosis Test pattern generation; high-level TPG; delay TPG; fault simulation; test generation for validation, debug and diagnosis; low-power TPG; TPG for memories and FPGAs. T4 On-Line Testing and Fault Tolerance T5 Test for Variability, Reliability and Defects Identification, characterization and modeling of defects, faults and degradation mechanisms; Defect based fault analysis, Simulation and ATPG of defect based faults; Reliability analysis and modeling techniques, FMEA and Physics of failure; Test for noise and uncertainty; Design for Reliability and Design for Variability and their impact on test; Test and reliability of redundant systems; Test and reliability issues in the presence of leakage; Challenges of ultra low-power design on test and reliability; Modeling and test techniques for physical sources of errors such as process, voltage and temperature variations; Error-resilient nano design systems. T6 Mixed-Signal/RF/MEMS Test and DfX Engineering Test techniques for mixed-signal, RF and multi-GHz electronics; Test techniques for embedded MEMS/bioMEMS/MOEMS sensors and actuators; assembly engineering for SiP/SoC/SoP/PoP; Failure modelling and analysis techniques; Defect characterization and fault modelling; Fault simulation and test generation algorithms; DfT/DfM/DfY/DfR (DfX) techniques; BIST; Test coverage metrics and statistical modeling; Effective defect screening techniques; Diagnosis and self-repair. |
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All manuscripts must be submitted electronically before September 7th, 2008, following the instructions on the conference Web page: The accepted file formats are PDF and Postscript. Manuscripts received in hard-copy form will not be processed. Papers can be submitted for either standard oral presentation or for interactive presentation. Standard oral presentations require novel and complete research work supported by experimental results, and are held in front of a full audience. Besides these, DATE will again include interactive presentations of novel ideas that may require additional research or lack experimental data. Presentations are given on a laptop in a face-to-face discussion area. Submissions should not exceed 6 pages in length for oral-presentation and 4 pages in length for interactive-presentation papers, and should be formatted as close as possible to the final format: A4 or letter sheets, double column, single spaced, Times or equivalent font of minimum 10pt (templates are available on the DATE Web site for your convenience). To permit blind review, submissions should not include the author names. Any submission not in line with the above rules will be discarded. All papers will be evaluated with regard to their suitability for the conference, originality and technical soundness. The Programme Committee reserves the right to accept interesting contributions that do not meet the criteria for standard oral presentations, as interactive presentations. |
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Submission deadline: September 7, 2008 |
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For
more information, visit us on the web at: http://www.date-conference.com/ |
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The Design, Automation and Test in Europe Conference and Exhibition (DATE 2009) is sponsored by the European Design and Automation Association, the EDA Consortium, the IEEE Computer Society (TTTC), (CEDA), ECSI, RAS and ACM SIGDA. |
IEEE
Computer Society- Test Technology Technical Council |
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TTTC
CHAIR PAST
CHAIR TTTC
1ST VICE CHAIR SECRETARY ITC GENERAL CHAIR TEST
WEEK COORDINATOR TUTORIALS
AND EDUCATION STANDARDS EUROPE MIDDLE
EAST & AFRICA STANDING
COMMITTEES ELECTRONIC
MEDIA |
PRESIDENT OF BOARD SENIOR
PAST CHAIR TTTC 2ND VICE CHAIR FINANCE IEEE DESIGN & TEST EIC TECHNICAL
MEETINGS TECHNICAL
ACTIVITIES ASIA
& PACIFIC LATIN
AMERICA NORTH
AMERICA COMMUNICATIONS INDUSTRY
ADVISORY BOARD |
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